|发表于: Sun 2007-06-10 15:49:07 发表主题: 思科公司招聘信息
|ASIC DFT Engineer
• ASIC DFT design and verification for JTAG boundary scan, scan, memory BIST and ATPG test vector generation.
• Design verification and debugging (both simulation based and C based), test coverage debugging and design automation scripting skills are required.
• strong problem solving skill and debugging skill.
• familiar with ASIC design flow from RTL Verilog coding, synthesis, timing to verification.
• Hands-on experience on ASIC or DFT design is a plus, but is not a requirement for new graduates.
• Verbal and written English communication skill is a must.
• MSEE/CS or equivalent, with 5+ year relevant experience, or BSEE/CS with 10+ year relevant experience. PhD degree is a plus.
• New grads or low experience but have great potential are also acceptable.
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